1. Field of the Invention:
The present invention relates to apparatus and methods for DC offset compensation especially in audio circuitry such as audio amplifier circuitry.
2. Description of the Related Art:
It is known that the presence of a DC offset voltage can cause problems in audio amplifier circuitry. In many applications an audio amplifier is driven with balanced positive and negative voltage supplies (e.g. +VDD and −VDD) so that the quiescent output voltage can be ground so that no AC coupling/DC blocking capacitor is required for the output signal when driving a grounded load. The presence of a DC offset voltage at the output of the audio amplifier can then lead to an offset voltage being suddenly imposed on the speaker load at power-up, or conversely suddenly removed at power-down, which may lead to an audio artefact such as an audible ‘pop’. Such an audio artefact is undesirable and should be reduced, or preferably avoided, if possible. Further the presence of a DC offset voltage can lead to power wastage due to the resultant quiescent load current having to be sourced from a supply by the driver amplifier. Such wastage is an issue for battery powered devices where unnecessary power consumption reduces battery life.
A DC offset may arise in an audio amplifier circuit in a number of ways. The driver amplifier may have a random input offset voltage. In many typical audio devices the audio signal to be amplified is received in digital form and is converted to an analogue signal by an audio digital-to-analogue convertor (DAC) for subsequent amplification. This audio DAC may also suffer from random DC offsets. Charge injection effects, for example in a switched-capacitor DAC, or mismatch between sink and source currents in a current-steering DAC may be sources of DC offset. Further, the DAC may be driven between a single voltage supply (e.g. +AVDD) and ground, and thus the analogue output signal from the DAC may require level shifting from say AVDD/2 before being input to the amplifier. Errors in the level shifting may also introduce DC offset. Whilst efforts are made to minimise DC offset it is difficult to completely eliminate DC offset in practical circuits.
It is therefore known to provide extra circuitry to eliminate, or reduce, DC offsets, i.e. to provide DC offset compensation circuitry, in integrated circuits for audio amplifiers. One known DC offset compensation system has a feedback path which comprises an analogue-to-digital convertor (ADC) and a digital integrator or low pass filter. The analogue output signal from the amplifier is compared to a reference signal which corresponds to the desired quiescent DC output voltage, say ground, and the resulting output error signal is converted to a digital signal by the ADC and then digitally filtered or integrated to give high gain at DC but attenuate audio-band components in the resultant digital correction signal output from the filter. The correction, or compensation, signal may be combined with the input digital audio signal prior to the audio DAC or alternatively converted into an analogue signal by a separate DAC and combined with the analogue input signal for the amplifier. In either case any DC offset present at the amplifier output is cancelled by the high DC gain negative feedback.
Such an offset compensation circuit provides an accurate and useful method of compensating for a DC offset. However the ADC is a relatively large component. In integrated circuits larger circuit area leads to higher cost. Further in some applications there may a limit on the size of chip, for example in chip scale packaging it may be wished to limit the size of chip to match that of a standard ball array to avoid any strain mismatch effects or reliability issues arising from overhang of the silicon die over the ball array. Thus in some applications the use of relatively large circuit components is undesirable. This may be exacerbated by the need to provide respective DC offset compensation for a plurality of audio outputs. Many typical devices, such as a portable audio device, may have audio signal outputs for headphones, an audio line out for driving speakers, for example via a docking station, an audio signal line to internal speakers and, in some cases, audio outputs for noise cancellation speakers. Some or all of these outputs may comprise a stereo pair of outputs. Thus a single chip, i.e. a single integrated circuit, may comprise a plurality of audio signal outputs each with its own associated amplifier circuitry and each having its own associated DC offset which requires compensation. Providing a separate DC offset compensation circuit as described for each audio signal line would involve a relatively significant amount of chip real estate.
The known DC offset compensation circuitry described above can advantageously be multiplexed between several different audio signal lines to compensate for the DC offset for each signal line in turn. Once a stable DC offset correction has been achieved for a signal line, the value of the correction signal can be latched for that signal line and the compensation circuitry used to compensate for the DC offset on another signal line. However, clearly this does mean that settling time for reaching steady state compensation for the chip as a whole is equal to the sum of the individual settling times for each of the audio signal outputs. In some applications a relatively fast settling time may be required and multiplexing the offset compensation circuit between multiple outputs may thus not be possible.